As Q4 goes into saturation, the output voltage Y will be pulled down to low. As Q2 conducts, the voltage at X will drop down and Q3 will be OFF, whereas voltage at Z will increase to turn ON Q4. Therefore D3 is forward biased and base current is supplied to transistor Q2 via R1 and D3. Therefore its collector voltage rises to $V_$.Ĭ) A and B both high: If both A and B are connected to then both diodes D1 and D2 will be reverse biased and do not conduct. Consider a 3-input TTL NAND gate with a simple output stage. Totem Pole means the addition of an active pull up the circuit in the output of the Gate which results in a reduction of propagation delay. Logicfamilies digitalelectronics digitalsystemdesign dsd ttlprevious year paper solution KEC 3022020-21SECTION CQUESTION 3(A)previous year paper solutio. However, the gate is capable of sinking current from a load, if only the load were connected differently. In this particular case, the way the load (LED) is connected to the output of the gate, the gate will only source current. This voltage is insufficient to forward bias B-E junction of Q2. Disadvantage of Single Output Stage TTL: Totem Pole Transistor-Transistor Logic (TTL). TTL gates equipped with totem-pole output circuitry are able to both source and sink load current. Hence D1 and D2 will conduct to force the voltage at point C to 0.7V. A and B are two inputs while Y is the output.Ī) A and B both low: both B-E junctions of Q1 are forward biased. REVIEW: A TTL NAND gate can be made by taking a TTL inverter circuit and adding another input. I am opting to show the open-collector versions for the sake of simplicity. The circuit diagram of a 2 input TTL NAND gate is as follows:Ī two input TTL NAND is shown above. Of course, both NAND and AND gate circuits may be designed with totem-pole output stages rather than open-collector.

Ttl nand gate with totem pole output